Suggested Courses

Learning FPGA Development

Learning FPGA Development

4.6
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Introduction to FPGA Design for Embedded Systems

Introduction to FPGA Design for Embedded Systems

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Hardware Description Languages for FPGA Design

Hardware Description Languages for FPGA Design

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Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

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Verification Series Part 3: UVM Essentials

Verification Series Part 3: UVM Essentials

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FPGA Softcore Processors and IP Acquisition

FPGA Softcore Processors and IP Acquisition

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FPGA Capstone: Building FPGA Projects

FPGA Capstone: Building FPGA Projects

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Introduction to VHDL for FPGA and ASIC design

Introduction to VHDL for FPGA and ASIC design

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VHDL Circuit Design and FPGAs with VIVADO and MODELSIM

VHDL Circuit Design and FPGAs with VIVADO and MODELSIM

4.3
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Zynq Training - Learn Zynq 7000 SOC device on Microzed FPGA

Zynq Training - Learn Zynq 7000 SOC device on Microzed FPGA

3.6
(164 ratings) 4,607 learners
2 hours 21 lectures Beginner
FPGA Embedded Design, Part 1 - Verilog

FPGA Embedded Design, Part 1 - Verilog

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Learn FPGA Design With VHDL (Intel/Altera)

Learn FPGA Design With VHDL (Intel/Altera)

4.7
(618 ratings) 4,376 learners
20 hours 70 lectures All Levels
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FPGA USB Device Design in VHDL - From First Principles

FPGA USB Device Design in VHDL - From First Principles

Building a FIFO-Based FPGA USB CDC Interface in VHDL Without Vendor IP Cores

Building a FIFO-Based FPGA USB CDC Interface in VHDL Without Vendor IP Cores

4.8 (4 ratings) 29 learners
28 hours 92 lectures Intermediate
1 week ago
Master FPGA design with VHDL : Sobel Filter Edge Detection

Master FPGA design with VHDL : Sobel Filter Edge Detection

Understand and build an edge detector based on Sobel filter from scratch in VHDL

Understand and build an edge detector based on Sobel filter from scratch in VHDL

5.0 (3 ratings) 16 learners
4 hours 28 lectures Beginner
1 week ago
Clock Domain Crossing (CDC) & FIFO Design

Clock Domain Crossing (CDC) & FIFO Design

Solve Metastability, Data Coherence & Loss with Verilog Labs, FIFO Depth Calculation & RTL Design. USE PROMO (PAY.13)

Solve Metastability, Data Coherence & Loss with Verilog Labs, FIFO Depth Calculation & RTL Design. USE PROMO (PAY.13)

5.0 (3 ratings) 107 learners
4 hours 16 lectures All Levels
3 weeks ago
FPGA Embedded Design, Part 2 - Basic FPGA Training

FPGA Embedded Design, Part 2 - Basic FPGA Training

Learn FPGA embedded application design starting with the basics and leaving with your own working hardware.

Learn FPGA embedded application design starting with the basics and leaving with your own working hardware.

4.4 (241 ratings) 2,527 learners
3 hours 59 lectures Intermediate
3 weeks ago
Formal Verification : Synopsys Formality Flow & Debug

Formal Verification : Synopsys Formality Flow & Debug

Master equivalence checking, logic cones, compare points, and real-world debugging with hands-on labs

Master equivalence checking, logic cones, compare points, and real-world debugging with hands-on labs

3.7 (3 ratings) 108 learners
2 hours 8 lectures All Levels
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PCIe Gen 7 – Complete Architecture, Protocol Masterclass

PCIe Gen 7 – Complete Architecture, Protocol Masterclass

Complete Guide to PCIe Gen 7: From Fundamentals to Advanced Design & Debug

Complete Guide to PCIe Gen 7: From Fundamentals to Advanced Design & Debug

4.2 (3 ratings) 149 learners
16 hours 29 lectures Intermediate
4 weeks ago
Xilinx VIVADO Beginner Course for FPGA Development in VHDL

Xilinx VIVADO Beginner Course for FPGA Development in VHDL

Learn how to Create VHDL Design,Simulation Testbench & Implementation with Xilinx VIVADO & FPGA: from Basic to Advanced.

Learn how to Create VHDL Design,Simulation Testbench & Implementation with Xilinx VIVADO & FPGA: from Basic to Advanced.

3.7 (60 ratings) 474 learners
5 hours 25 lectures All Levels
1 month ago
Communication series P2 : AMBA APB in Verilog

Communication series P2 : AMBA APB in Verilog

Step by Step Guide from Scratch

Step by Step Guide from Scratch

4.3 (35 ratings) 262 learners
4 hours 66 lectures Intermediate
2 months ago
FPGA Embedded Design, Part 3 - EDA Tools

FPGA Embedded Design, Part 3 - EDA Tools

Learn FPGA embedded application design with four different tools.

Learn FPGA embedded application design with four different tools.

4.1 (56 ratings) 1,043 learners
3 hours 74 lectures Intermediate
2 months ago
High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

Logic Design with Vitis-HLS

Logic Design with Vitis-HLS

4.6 (186 ratings) 2,380 learners
9 hours 102 lectures Intermediate
2 months ago
Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Embedded System Accelerators with Vitis and HLS

Embedded System Accelerators with Vitis and HLS

4.2 (220 ratings) 1,943 learners
9 hours 98 lectures Beginner
2 months ago
Video Processing with FPGA

Video Processing with FPGA

Implementing different Computer Vision Algorithm on Xilinx Zynq FPGA with VIVADO High Level Synthesis & SDK

Implementing different Computer Vision Algorithm on Xilinx Zynq FPGA with VIVADO High Level Synthesis & SDK

3.6 (131 ratings) 1,200 learners
4 hours 30 lectures All Levels
2 months ago